CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.

Publication Year: 2008
Imprint: Springer Netherlands
Format: H
Weight (Gram): 1050