Variation Tolerant On-Chip Interconnects

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

Publication Year: 2012
Imprint: Springer New York
Format: P
Weight (Gram): 290